射频识别技术是20世纪90年代开始兴起的一种自动识别技术，他是指通过检测目标物体对射频电磁场的扰动从而获得其相关特征信息的一种非接触式探测技术。他可用于识别高速运动物体并可同时识别多个射频卡，而且操作快捷方便，不怕油渍、灰尘污染等恶劣的环境。对他的研究方向很多，其中一个重要部分就是时钟恢复电路的研究。时钟恢复电路是通讯系统模拟前端中的一个关键电路，他的主要任务是：从接收到的带有噪声的二进制数据流中恢复出与数据同步的时钟信号，然后对数据进行判决再生，以减少或消除数据在传输过程中受到的噪声和干扰。 所以本论文在调研了有关射频识别和时钟恢复电路的原理和发展后，拟研究和实现一个能够克服场区能量不定的困难，而且体积小、功耗低的用于射频识别的CDR电路，并通过Hspice模拟、Cadence模拟确定其电路参数，绘制出其仿真结果图，用Virtuoso Layout Editor设计其版图。

RFID is an auto-identification technique rising in the 90s of 20 century. It realizes data acquisition and communication by means of electromagnetic coupling or electromagnetic coincidence between radio signals. It can be used to identify high speed objects and can identify multiple RF cards at the same time. It can get over many tough environments. So the study on it is gradually increasing. Clock Recovery Circuit is a key circuit for the front end of analog circuit for communication. It gets the clock signal from the binary data stream with noise. In this paper, the development of RFID is introduced at first. After that, the history of clock recovery circuits is presented. Then the basic concept of inverter and OR-Gate logic CMOS Circuit is disused. Then we use the Hspice and Cadence to design circuit which is small can overcome the instability of energy, simulate the parameter of each MOSFET. At last the layout is drawn by use of Virtuoso, and given design rule check. The layout netlist is extracted.