晶体管是现代集成电路不可缺少的半导体电子器件，半导体结是目前所有晶体管所必需的，是影响器件性能的重要组成部分。然而随着器件尺寸的不断减小，制备高质量的结将变成越来越难的事情。无结硅纳米线场效应晶体管首次在2009年提出，其源区、漏区与沟道区的掺杂浓度是恒定且均一的，这将有效的解决上述问题。Ge因其相比于Si具有更高的载流子迁移率而受到了广泛的研究。　　　Ge纳米线无结FET的I-V特性与传统的有结FET的特性曲线非常的相似，但由于两者的工作机理的不同，Ge纳米线无结FETs的性能将与传统的有结FET器件有所不同，本研究将围绕着这一问题进行Ge纳米线p-FETs的性能模拟研究，而对于Ge纳米线n-FETs，由于费米能级钉扎效应，n-FETs的源漏接触表现为肖特基接触，这制约着器件的性能，因此我们对其源漏接触进行工艺探讨。　　　利用Sentaurus TCAD模拟软件对Ge纳米线无结p-FETs的性能进行模拟研究，p-FETs的结构尺寸主要包括沟道的宽度、高度、长度以及栅介质氧化层的厚度，对不同结构尺寸的器件进行模拟。通过模拟我们在Ge纳米线无结p-FETs中得到了高开关电流比1×108的器件，并对不同器件结构尺寸对器件的影响进行了分析讨论。　　　沟道的掺杂浓度，包括均匀和非均匀掺杂的情况。针对均匀掺杂的沟道，探讨了掺杂浓度对器件性能的影响。模拟结果表明，低浓度的沟道使得沟道中的载流子能够较容易的被栅极电压所耗尽，实现关断的状态，但低掺杂浓度值的器件使得开态电流值会减小。非均匀掺杂主要是通过改变沟道的掺杂分布，得到了具有更大开关电流比的器件。　　　根据模拟分析，我们进一步探讨实现Ge纳米线无结FETs常关的可能性，获得了实现器件常关的参数要求。综合器件的影响参数，对器件的性能进行了敏感度分析，提出器件中沟道的高度，栅介质氧化层厚度，掺杂浓度对其性能影响最为显著，是器件制备工艺中必须优先考虑的方向。　　　针对Ge纳米线n-FETs的源漏接触问题，研究了金属和n-Ge接触的肖特基势垒宽度和高度进行调控的方法。采用线性传输线模型（TLM）来测定金属与n-Ge的接触电阻率，研究了不同P注入剂量下的n型Ge与NiGe合金的接触电阻率。在5×1015cm-2的注入剂量的情况下得到了电阻率为2×10-5Ωcm2的接触界面。同时我们控制NiGe形成的退火温度，研究了不同退火温度下的界面接触电阻率，在450℃，30s的较好的退火条件下获得了较优的界面接触，通过进一步的NiGe合金的XRD分析，解释了NiGe相和接触电阻率之间的关系。为进一步提高Ge中的掺杂浓度，利用P离子注入和AsH3扩散的方法实现Ge的n型共掺杂，SIMS检测表明As扩散后在Ge的表面实现了超过1020cm-3的掺杂浓度值,接触电阻率达到1.65×10-5Ωcm2。　　　在肖特基势垒高度调控方面，研究了在金属与n-Ge之间引入薄介质层的方法从而形成金属-介质-半导体的MIS结构。在研究中我们引入不同的介质（Al2O3，TiO2，GeOx），得到了不同MIS结构的I-V特性曲线，利用热电子发射理论从中提取出了金属与Ge之间的肖特基势垒高度（SBH）随介质厚度的关系。结果表明，接触界面的SBH能从0.6 eV左右降到0.3 eV左右，但不同介质的调控作用存在着差异。对MIS接触结构的理论分析表明，SBH的降低并不能一定代表接触电阻率的降低，介质的导带偏移CBO对接触电阻率的影响很大，这方面需进行进一步的研究。

Transistors is indispensable semiconductor electronic devices in modern integrated circuit.Currently semiconductor junction ,which is an important influencing part of the device performance,is necessary to all transistors.With the decreasing size of the device,It will be increasingly difficult to fabricate high quality junction.In 2009,silicon nanowire junctionless field-effect transitors(FET) are proposed,the source,drain and channel region of the device are doped uniformly,It will solve the problem effectively.Compared to Si,Ge has higher carriers mobility,which makes Ge attracts widely study.　　　　Germanium nanowire junctionless FETs have the similar I-V characteristic with traditional FET with junction,but they have different operation mechanism,the performance will be different from the traditional FET.In this study,we carry on simulation study on the Ge naowire p-FET,but for n-FET,due to the fermi level pining effect, the source and drain contacts of n-FET are schottky contacts,which restricts the performance of the device,this study will conduct the technical study of the source and drain contacts.　　　　Sentaurus TCAD simulation software are used in the simulation study of the performance of Ge nanowire junctionless p-FETs. The size of p-FETs mainly includes channel width,height,length and thickness of the gate dielectric oxide layer, simulation are conducted on the different dimensions of the devices.In the simulation ,we can get device with the Ion/Ioff=1×108. Devices with different sizes’s influence on the performance of devices are also discussed.　　　Doping concentration of channel.including the case of uniform and non-uniform doping, for uniformly doped channel, we discuss the effect of doping concentration on device performance,the simulation results show that channel with low doping concentration makes the carriers in the channel is easier to be depleted by the gate voltage,and the device achieve the off-state,but the on-state current of devices with low doping concentration decreases.For non-uniform doping situation,compared to uniform doping situation ,we get devices with bigger Ion/Ioff by changing the doping profile.　　　According to the simulation results, we further explore the possibility of normally-off for Ge nanowire junctionless FETs and get the demands of the parameters to achieve the normally-off devices.Considering all the parameters of the devices,we conduct a sensitivity analysis of the devices’ performance, the results indicate that channel height,the gate dielectric oxide thickness and doping concentration influent significantly on the device performance.,which provide priority direction for the device fabrication process.　　　For the source and drain contact of the Ge nanowire n-FETs, in the study,we modulate the width and height of the schottky barrier between metal and n-Ge. Transmission Line Model(TLM) is adopted to measure the specific contact resistivity , under different P implant doses are measured and get =2×10-5Ωcm2 in the conditon of implant dose is 5×1015cm-2. Annealing temperature are studied to form NiGe and we find that 450 ℃, 30s annealing condition is a good choice to get a low ,XRD analysis are carried out to study the phase of the NiGe alloy and find the relationship between the and NiGe phase.In order to improve the doping concentration of n-Ge further, P and As co-doping are used, SIMS analysis shows that the surface concentration can exceed 1020cm-3,=1.65×10-5Ωcm2 .　　　For the modulation of decreasing schottky barrier height (SBH),we study the metal insulator semiconductor (MIS) contacts structure ,different insulators (Al2O3，TiO2，GeOx) are introduced to get a different MIS structure, I-V characteristic is got and by using thermionic emission theory,we extract SBH relationship with the thickness of the insulator,the results show that SBH can decrease to about 0.3 eV from 0.6 eV and modulation effect differs between the different insulator.Theoretical analysis shows that the decrease of SBH can not represent the decrease of ,conduction band offset (CBO) affect greatly,It needs more efforts to study in this area.