随着集成电路工艺进入纳米时代，功耗对电路系统性能产生的影响越来越大。低功耗设计技术已成为集成电路设计领域研究的热点，而晶体管级的功耗优化技术正对该研究领域产生深刻影响。所以，本文对当前低功耗设计的主流技术进行简要介绍，并集中对晶体管级低功耗设计方法作更加深入的探讨。晶体管级功耗优化方法具有优化粒度高，效果好的优点，但存在算法复杂，运行成本高的瓶颈。就此，本文在快速功耗及时延模拟方法的基础上，介绍一种基于跳变率和拓扑结构调整的晶体管级动态功耗优化方法以及一种基于快速模拟器和灵敏度刷新的静态功耗优化方法。两种晶体管级优化技术都在可接受的成本下实现了更好的功耗优化效果，是低功耗设计技术的最新发展。同时，本文给出了两种方法优化电路的实例及实验数据。

Power has increasing impact on the performance of IC as Nanometer technology is widely used in IC production. Low-power design has become one of the focuses in IC design, where transistor-level power reduction has significant influence. In this paper, several power optimization methodologies are briefly introduced and transistor-level methodologies is then discussed in detail. Compared with other methodologies, transistor-level technology produces better optimization results, but large runtime and cost has limited its application. In respect of these problems, an active power reduction method based on switching activity and topological structure generation as well as a leakage reduction method based on fast simulation and sensitivity update is introduced in this paper with their experiment results. Both of the methods achieve great reduction of active power or leakage respectively.